Issued Patents 2023
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11832451 | High density ferroelectric random access memory (FeRAM) devices and methods of fabrication | Debraj Guhabiswas, Maria Isabel Perez, Jason Y. Wu, James David Clarkson, Gabriel Antonio Paulius Velarde +4 more | 2023-11-28 |
| 11769790 | Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2023-09-26 |
| 11764790 | Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme | Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes +1 more | 2023-09-19 |
| 11764190 | 3D stacked compute and memory with copper pillars | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-19 |
| 11758738 | Integration of ferroelectric memory devices with transistors | Sasikanth Manipatruni, Rajeev Kumar Dokania, Gaurav Thareja, Amrita Mathuriya | 2023-09-12 |
| 11742860 | Fabrication of a majority logic gate having non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2023-08-29 |
| 11744081 | Ferroelectric device film stacks with texturing layer which is part of a bottom electrode, and method of forming such | Niloy Mukherjee, Sasikanth Manipatruni, James David Clarkson, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde +1 more | 2023-08-29 |
| 11716858 | Ferroelectric device film stacks with texturing layer which is part of a bottom electrode and a barrier, and method of forming such | Niloy Mukherjee, Sasikanth Manipatruni, James David Clarkson, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde +1 more | 2023-08-01 |
| 11711083 | Majority gate based low power ferroelectric based adder with reset mechanism | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Guarav Thareja +1 more | 2023-07-25 |
| 11705906 | Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic | Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes +1 more | 2023-07-18 |
| 11659714 | Ferroelectric device film stacks with texturing layer, and method of forming such | Niloy Mukherjee, Sasikanth Manipatruni, James David Clarkson, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde +1 more | 2023-05-23 |
| 11641747 | Integration of a ferroelectric memory device with a transistor | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-05-02 |
| 11637090 | Method of forming a 3D stacked compute and memory | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-04-25 |
| 11616507 | Ferroelectric based latch | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-03-28 |