Issued Patents 2022
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532640 | Method for manufacturing a three-dimensional memory | Han-Jong Chia, Chung-Te Lin, Meng-Han Lin, Sheng-Chen Wang | 2022-12-20 |
| 11527553 | Three-dimensional memory device and method | Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin, Chung-Te Lin | 2022-12-13 |
| 11508827 | Air spacer for a gate structure of a transistor | Yi-Hsiu Liu, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen | 2022-11-22 |
| 11508736 | Method for forming different types of devices | Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen | 2022-11-22 |
| 11502005 | Semiconductor devices and methods of forming the same | Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen | 2022-11-15 |
| 11502182 | Selective gate air spacer formation | Chih-Hsin Yang, Yen-Ming Chen, Tsung-Lin Lee, Wei-Yang Lee, Dian-Hau Chen | 2022-11-15 |
| 11495618 | Three-dimensional memory device and method | Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin, Chung-Te Lin | 2022-11-08 |
| 11476352 | Conformal transfer doping method for fin-like field effect transistor | Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Yen-Ming Chen | 2022-10-18 |
| 11456295 | Air gap formation between gate spacer and epitaxy structure | Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Yen-Ming Chen | 2022-09-27 |
| 11449445 | Transaction-based hybrid memory | Xiaobing Lee | 2022-09-20 |
| 11437469 | Reducing parasitic capacitance in semiconductor devices | Chia-Ta Yu, Hsiao-Chiu Hsu | 2022-09-06 |
| 11423966 | Memory array staircase structure | Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin, Chung-Te Lin | 2022-08-23 |
| 11362199 | Semiconductor device and method | I-Hsieh Wong, Yen-Ting Chen, Wei-Yang Lee, Yen-Ming Chen | 2022-06-14 |
| 11355641 | Merged source/drain features | Chun-An Lin, Wei-Yuan Lu, Tzu-Ching Lin, Li-Li Su | 2022-06-07 |
| 11355516 | Three-dimensional memory device and method | Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin | 2022-06-07 |
| 11355400 | Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET | Yen-Ting Chen, Wei-Yang Lee, Yen-Ming Chen | 2022-06-07 |
| 11296077 | Transistors with recessed silicon cap and method forming same | Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee +1 more | 2022-04-05 |
| 11289574 | Methods of forming epitaxial source/drain features in semiconductor devices | Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Yen-Ming Chen | 2022-03-29 |
| 11257928 | Method for epitaxial growth and device | Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Yen-Ming Chen | 2022-02-22 |
| 11217490 | Source/drain features with an etch stop layer | Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen | 2022-01-04 |
| 11217486 | Semiconductor device and method | Cheng-Yu Yang, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen | 2022-01-04 |