Issued Patents 2022
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532640 | Method for manufacturing a three-dimensional memory | Han-Jong Chia, Chung-Te Lin, Feng-Cheng Yang, Meng-Han Lin | 2022-12-20 |
| 11532343 | Memory array including dummy regions | Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Yu-Ming Lin | 2022-12-20 |
| 11527553 | Three-dimensional memory device and method | Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin | 2022-12-13 |
| 11515313 | Gated ferroelectric memory cells for memory cell array and methods of forming the same | Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Yu-Ming Lin | 2022-11-29 |
| 11495618 | Three-dimensional memory device and method | Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin | 2022-11-08 |
| 11476352 | Conformal transfer doping method for fin-like field effect transistor | Sai-Hooi Yeong, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen | 2022-10-18 |
| 11444069 | 3D semiconductor package including memory array | Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Yu-Ming Lin | 2022-09-13 |
| 11423966 | Memory array staircase structure | Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin | 2022-08-23 |
| 11407083 | Polishing head, chemical-mechanical polishing system and method for polishing substrate | Shu-Bin Hsu, Ren-Guei Lin, Feng-Inn Wu, Jung-Yu Li | 2022-08-09 |
| 11404099 | Using split word lines and switches for reducing capacitive loading on a memory system | Meng-Han Lin, Chia-En Huang, Yi-Ching Liu | 2022-08-02 |
| 11355516 | Three-dimensional memory device and method | Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Chung-Te Lin | 2022-06-07 |