Issued Patents 2020
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878914 | Memory device with compensation for program speed variations due to block oxide thinning | Ashish Baraskar, Vinh Diep | 2020-12-29 |
| 10854300 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Vinh Diep, Zhengyi Zhang | 2020-12-01 |
| 10811109 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Vinh Diep, Yingda Dong | 2020-10-20 |
| 10804282 | Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same | Ashish Baraskar, Fei Zhou, Raghuveer S. Makala | 2020-10-13 |
| 10762973 | Suppressing program disturb during program recovery in memory device | Zhengyi Zhang | 2020-09-01 |
| 10741253 | Memory device with compensation for erase speed variations due to blocking oxide layer thinning | Ashish Baraskar, Vinh Diep | 2020-08-11 |
| 10706941 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Vinh Diep, Zhengyi Zhang | 2020-07-07 |
| 10692877 | Non-volatile memory with silicided bit line contacts | Simon S. Chan, Hidehiko Shiraiwa, Lei Xue | 2020-06-23 |
| 10685979 | Three-dimensional memory device with drain-select-level isolation structures and method of making the same | Wei Zhao, Yanli Zhang, James Kai | 2020-06-16 |
| 10685978 | Three-dimensional memory device with drain-select-level isolation structures and method of making the same | Wei Zhao, Yanli Zhang, James Kai | 2020-06-16 |
| 10665313 | Detecting short circuit between word line and source line in memory device and recovery method | Henry Chin, Jian Chen | 2020-05-26 |
| 10665301 | Memory device with compensation for program speed variations due to block oxide thinning | Ashish Baraskar, Vinh Diep | 2020-05-26 |
| 10665299 | Memory device with channel discharge before program-verify based on data state and sub-block position | Hong-Yan Chen | 2020-05-26 |
| 10636501 | Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line | Han-Ping Chen, Vinh Diep, Changyuan Chen | 2020-04-28 |
| 10629272 | Two-stage ramp up of word line voltages in memory device to suppress read disturb | Hong-Yan Chen, Wei Zhao | 2020-04-21 |
| 10629616 | Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer | James Kai, Murshed Chowdhury, Johann Alsmeier | 2020-04-21 |
| 10566059 | Three dimensional NAND memory device with drain select gate electrode shared between multiple strings | Vinh Diep, Henry Chin, Changyuan Chen | 2020-02-18 |
| 10541035 | Read bias adjustment for compensating threshold voltage shift due to lateral charge movement | Han-Ping Chen, Chung-Yao Pai, Yingda Dong | 2020-01-21 |