| 10854304 |
Apparatus and methods for seeding operations concurrently with data line set operations |
Jun Xu |
2020-12-01 |
| 10811109 |
Multi-pass programming process for memory device which omits verify test in first program pass |
Ashish Baraskar, Ching-Huang Lu, Vinh Diep |
2020-10-20 |
| 10755788 |
Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses |
Peter Rabkin, Kwang Ho Kim, Masaaki Higashitani |
2020-08-25 |
| 10748627 |
Reducing neighbor word line interference in a two-tier memory device by modifying word line programming order |
Hong-Yan Chen, Zhengyi Zhang |
2020-08-18 |
| 10734408 |
Ferroelectric non-volatile memory |
Yangyin Chen, Yukihiro Sakotsubo |
2020-08-04 |
| 10685723 |
Reducing read disturb in two-tier memory device by modifying duration of channel discharge based on selected word line |
Hong-Yan Chen, Wei Zhao |
2020-06-16 |
| 10650898 |
Erase operation in 3D NAND flash memory including pathway impedance compensation |
Peter Rabkin, Kwang Ho Kim, Masaaki Higashitani |
2020-05-12 |
| 10636500 |
Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge |
Hong-Yan Chen, Wei Zhao |
2020-04-28 |
| 10636488 |
Multi-sensing scan for cross-temperature mitigation |
Lei Lin, Wei Zhao, Henry Chin |
2020-04-28 |
| 10559588 |
Three-dimensional flat inverse NAND memory device and method of making the same |
Yangyin Chen, James Kai |
2020-02-11 |
| 10541035 |
Read bias adjustment for compensating threshold voltage shift due to lateral charge movement |
Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai |
2020-01-21 |
