Issued Patents 2020
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878914 | Memory device with compensation for program speed variations due to block oxide thinning | Ching-Huang Lu, Ashish Baraskar | 2020-12-29 |
| 10854300 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Zhengyi Zhang | 2020-12-01 |
| 10811109 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Ching-Huang Lu, Yingda Dong | 2020-10-20 |
| 10741253 | Memory device with compensation for erase speed variations due to blocking oxide layer thinning | Ching-Huang Lu, Ashish Baraskar | 2020-08-11 |
| 10706941 | Multi-state programming in memory device with loop-dependent bit line voltage during verify | Ching-Huang Lu, Zhengyi Zhang | 2020-07-07 |
| 10665301 | Memory device with compensation for program speed variations due to block oxide thinning | Ching-Huang Lu, Ashish Baraskar | 2020-05-26 |
| 10636501 | Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line | Han-Ping Chen, Ching-Huang Lu, Changyuan Chen | 2020-04-28 |
| 10566059 | Three dimensional NAND memory device with drain select gate electrode shared between multiple strings | Ching-Huang Lu, Henry Chin, Changyuan Chen | 2020-02-18 |