Issued Patents 2020
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10847452 | Non-volatile memory with capacitors using metal under signal line or above a device capacitor | Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Peter Rabkin | 2020-11-24 |
| 10840260 | Through-array conductive via structures for a three-dimensional memory device and methods of making the same | James Kai, Murshed Chowdhury, Fumiaki Toyama, Johann Alsmeier | 2020-11-17 |
| 10840259 | Three-dimensional memory device including liner free molybdenum word lines and methods of making the same | Peter Rabkin, Raghuveer S. Makala | 2020-11-17 |
| 10825827 | Non-volatile memory with pool capacitor | Mohan Dunga, James Kai, Venkatesh Ramachandra, Piyush Dak, Luisa Lin | 2020-11-03 |
| 10818685 | Non-volatile memory with pool capacitor | Mohan Dunga, James Kai, Venkatesh Ramachandra, Piyush Dak, Luisa Lin | 2020-10-27 |
| 10789992 | Non-volatile memory with capacitors using metal under pads | Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Peter Rabkin | 2020-09-29 |
| 10763271 | Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same | Peter Rabkin, Jayavel Pachamuthu | 2020-09-01 |
| 10755788 | Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses | Peter Rabkin, Kwang Ho Kim, Yingda Dong | 2020-08-25 |
| 10726926 | Hot-cold VTH mismatch using VREAD modulation | Dae Wung Kang, Peter Rabkin | 2020-07-28 |
| 10658381 | Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same | Jixin Yu, Fumiaki Toyama, Tong Zhang, Chun Ge, Xin Li +1 more | 2020-05-19 |
| 10650898 | Erase operation in 3D NAND flash memory including pathway impedance compensation | Peter Rabkin, Kwang Ho Kim, Yingda Dong | 2020-05-12 |