Issued Patents 2020
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10847424 | Method for forming a nanowire device | Kandabara Tapily, Gerrit J. Leusink | 2020-11-24 |
| 10833078 | Semiconductor apparatus having stacked gates and method of manufacture thereof | Anton J. deVilliers, Kandabara Tapily, Subhadeep Kal, Gerrit J. Leusink | 2020-11-10 |
| 10770479 | Three-dimensional device and method of forming the same | Anton J. deVilliers, Kandabara Tapily, Jodi Grzeskowiak, Kai-Hung Yu | 2020-09-08 |
| 10734224 | Method and device for incorporating single diffusion break into nanochannel structures of FET devices | Anton J. deVilliers | 2020-08-04 |
| 10714391 | Method for controlling transistor delay of nanowire or nanosheet transistor devices | Subhadeep Kal, Anton J. deVilliers | 2020-07-14 |
| 10685887 | Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device | Subhadeep Kal | 2020-06-16 |
| 10665779 | Methods for additive formation of a STT MRAM stack | Noel Russell | 2020-05-26 |
| 10665672 | Method of preventing bulk silicon charge transfer for nanowire and nanoslab processing | Anton J. deVilliers | 2020-05-26 |
| 10586765 | Buried power rails | Anton J. deVilliers, Kandabara Tapily | 2020-03-10 |
| 10580691 | Method of integrated circuit fabrication with dual metal power rail | Soo Doo Chae, Kaoru Maekawa, Nicholas Joy, Gerrit J. Leusink, Kai-Hung Yu | 2020-03-03 |
| 10573655 | Three-dimensional semiconductor device and method of fabrication | Anton J. deVilliers | 2020-02-25 |
| 10541174 | Interconnect structure and method of forming the same | Soo Doo Chae, Gerrit J. Leusink, Robert D. Clark, Kai-Hung Yu | 2020-01-21 |
| 10529830 | Extension region for a semiconductor device | Kandabara Tapily, Nihar Mohanty, Anton J. deVilliers | 2020-01-07 |