Issued Patents 2020
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10685866 | Fin isolation to mitigate local layout effects | Huimei Zhou, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert R. Robison +2 more | 2020-06-16 |
| 10679901 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Shogo Mochizuki, Ruqiang Bao | 2020-06-09 |
| 10672910 | Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) | Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene | 2020-06-02 |
| 10658224 | Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects | Huimei Zhou, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu +1 more | 2020-05-19 |
| 10586767 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Ruqiang Bao +2 more | 2020-03-10 |
| 10535517 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Ruqiang Bao, Dechao Guo | 2020-01-14 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Chun-Chen Yeh | 2020-01-14 |