Issued Patents 2020
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10854607 | Isolation well doping with solid-state diffusion sources for finFET architectures | Chia-Hong Jan, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-12-01 |
| 10854757 | FINFET based junctionless wrap around structure | Rahul Ramaswamy, Hsu-Yu Chang, Chia-Hong Jan, Neville L. Dias, Roman W. Olac-Vaw +1 more | 2020-12-01 |
| 10847456 | Antifuse element using spacer breakdown | Ting Chang, Chia-Hong Jan | 2020-11-24 |
| 10847544 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-11-24 |
| 10840341 | Semiconductor devices, radio frequency devices and methods for forming semiconductor devices | Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer | 2020-11-17 |
| 10811751 | Monolithic splitter using re-entrant poly silicon waveguides | Rahul Ramaswamy, Chia-Hong Jan, Neville L. Dias, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2020-10-20 |
| 10797047 | Gate isolation in non-planar transistors | Leonard P. GULER, Gopinath Bhimarasetti, Vyom Sharma, Christopher P. Auth | 2020-10-06 |
| 10784378 | Ultra-scaled fin pitch having dual gate dielectrics | Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Chia-Hong Jan, Everett S. Cassidy-Comfort | 2020-09-22 |
| 10763209 | MOS antifuse with void-accelerated breakdown | Roman W. Olac-Vaw, Chia-Hong Jan, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy +2 more | 2020-09-01 |
| 10761264 | Transmission lines using bending fins from local stress | Rahul Ramaswamy, Chia-Hong Jan, Neville L. Dias, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2020-09-01 |
| 10756210 | Depletion mode gate in ultrathin FINFET based architecture | Chia-Hong Jan, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Roman W. Olac-Vaw +1 more | 2020-08-25 |
| 10741640 | Dielectric and isolation lower Fin material for Fin-based electronics | Chia-Hong Jan | 2020-08-11 |
| 10707346 | High-voltage transistor with self-aligned isolation | Chia-Hong Jan | 2020-07-07 |
| 10692888 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-06-23 |
| 10692771 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Chia-Hong Jan, Pei-Chi Liu | 2020-06-23 |
| 10658361 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park | 2020-05-19 |
| 10643999 | Doping with solid-state diffusion sources for finFET architectures | Chia-Hong Jan, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-05-05 |
| 10559688 | Transistor with thermal performance boost | Chen-Guan Lee, Joodong Park, Chia-Hong Jan, Hsu-Yu Chang | 2020-02-11 |