Issued Patents 2020
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879393 | Methods of fabricating semiconductor devices having gate structure with bent sidewalls | Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang | 2020-12-29 |
| 10854607 | Isolation well doping with solid-state diffusion sources for finFET architectures | Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-12-01 |
| 10847544 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-11-24 |
| 10825907 | Self-aligned contact and manufacturing method thereof | Tung Ying Lee, Chih Chieh Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo | 2020-11-03 |
| 10797048 | Semiconductor device and a method for fabricating the same | Hsiang-Ku Shen, Chih Wei Lu, Janet Chen | 2020-10-06 |
| 10755970 | Semiconductor device structures | Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang | 2020-08-25 |
| 10734283 | Semiconductor device and a method for fabricating the same | Hui-Chi Chen, Hsiang-Ku Shen | 2020-08-04 |
| 10692888 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2020-06-23 |
| 10665673 | Integrated circuit structure with non-gated well tap cell | Jiefeng Lin, Chih-Yung Lin | 2020-05-26 |
| 10658361 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Chia-Hong Jan, Joodong Park, Walid M. Hafez | 2020-05-19 |
| 10651289 | Semiconductor device and a method for fabricating the same | Yao-De Chiou, Janet Chen | 2020-05-12 |
| 10643999 | Doping with solid-state diffusion sources for finFET architectures | Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-05-05 |
| 10529824 | Semiconductor device and method for fabricating the same | Yao-De Chiou, Hui-Chi Chen | 2020-01-07 |