Issued Patents 2019
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10290635 | Buried interconnect conductor | Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2019-05-14 |
| 10290737 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz | 2019-05-14 |
| 10283508 | Semiconductor device and fabricating the same | Ting-Hung Hsu | 2019-05-07 |
| 10269798 | Semiconductor device and manufacturing method thereof | Chih-Hao Wang, Chih-Liang Chen, Shi Ning Ju | 2019-04-23 |
| 10269964 | FinFETs with source/drain cladding | Ka-Hing Fung, Zhiqiang Wu | 2019-04-23 |
| 10269933 | Recessing STI to increase Fin height in Fin-first process | Guan-Lin Chen | 2019-04-23 |
| 10269901 | Semiconductor liner of semiconductor device | Chih-Hao Wang, Carlos H. Diaz | 2019-04-23 |
| 10269803 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2019-04-23 |
| 10211307 | Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement | Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng | 2019-02-19 |
| 10181426 | Etch profile control of polysilicon structures of semiconductor devices | Chih-Hao Wang, Kuan-Ting Pan | 2019-01-15 |
| 10170365 | Wrap around silicide for FinFETs | Chi-Wen Liu, Ying-Keung Leung | 2019-01-01 |
| 10170592 | Integrated circuit structure with substrate isolation and un-doped channel | Guan-Lin Chen | 2019-01-01 |