HL

Hsien-Wen Liu

NT Nanya Technology: 11 patents #2 of 28Top 8%
TSMC: 5 patents #407 of 3,065Top 15%
Overall (2019): #3,331 of 560,194Top 1%
16
Patents 2019

Issued Patents 2019

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
10510690 Wafer level package (WLP) and method for forming the same Shin-Puu Jeng 2019-12-17
10437499 Hybrid memory system and method of operating the same Chung-Hsun Lee 2019-10-08
10380024 DRAM and method of operating the same in an hierarchical memory system Chung-Hsun Lee 2019-08-13
10354988 Using metal-containing layer to reduce carrier shock in package formation Shin-Puu Jeng, Yi-Jou Lin 2019-07-16
10354713 DRAM and method for determining binary logic using a test voltage level Chung-Hsun Lee 2019-07-16
10347574 Integrated fan-out packages Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Chih-Hsien Lin, Shih-Ting Hung +1 more 2019-07-09
10338831 System and method for preserving data in volatile memory Chung-Hsun Lee 2019-07-02
10332580 DRAM and method for determining binary logic using a test voltage level Chung-Hsun Lee 2019-06-25
10332579 DRAM and method for operating the same Chung-Hsun Lee 2019-06-25
10297304 Memory device and operating method thereof Chung-Hsun Lee 2019-05-21
10290605 Fan-out package structure and method for forming the same Shin-Puu Jeng, Po-Yao Chuang, Tzu-Jui Fang, Yi-Jou Lin 2019-05-14
10290590 Stacked semiconductor device and method of manufacturing the same Shin-Puu Jeng, Tzu-Jui Fang, Hsi-Kuei Cheng, Chih-Kang Han, Yi-Jen Lai +1 more 2019-05-14
10276228 DRAM and method of operating the same Chung-Hsun Lee 2019-04-30
10269445 Memory device and operating method thereof Chung-Hsun Lee 2019-04-23
10262719 DRAM and refresh method thereof Chung-Hsun Lee 2019-04-16
10236035 DRAM memory device adjustable refresh rate method to alleviate effects of row hammer events Chung-Hsun Lee 2019-03-19