Issued Patents 2019
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10276687 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki | 2019-04-30 |
| 10256161 | Dual work function CMOS devices | Muthumanickam Sankarapandian, Koji Watanabe | 2019-04-09 |
| 10256289 | Efficient metal-insulator-metal capacitor fabrication | Kisup Chung, Isabel C. Estrada-Raygoza, Chi-Chun Liu, Yann Mignot, Hao Tang | 2019-04-09 |
| 10256159 | Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device | Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki | 2019-04-09 |
| 10249540 | Dual channel CMOS having common gate stacks | Takashi Ando, Choonghyun Lee, Vijay Narayanan | 2019-04-02 |
| 10249758 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh | 2019-04-02 |
| 10236219 | VFET metal gate patterning for vertical transport field effect transistor | Brent A. Anderson, Ruqiang Bao, Kangguo Cheng, Choonghyun Lee, Junli Wang | 2019-03-19 |
| 10229856 | Dual channel CMOS having common gate stacks | Takashi Ando, Choonghyun Lee, Vijay Narayanan | 2019-03-12 |
| 10229986 | Vertical transport field-effect transistor including dual layer top spacer | Choonghyun Lee, Alexander Reznicek, Christopher J. Waskiewicz | 2019-03-12 |
| 10229975 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Choonghyun Lee, Shogo Mochizuki, Koji Watanabe | 2019-03-12 |
| 10170316 | Controlling threshold voltage in nanosheet transistors | Paul C. Jamison | 2019-01-01 |