Issued Patents 2018
Showing 76–100 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9940135 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-04-10 |
| 9928173 | Conditional inclusion of data in a transactional memory read set | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-27 |
| 9928064 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-03-27 |
| 9921843 | Predictive fetching and decoding for selected instructions | Valentina Salapura | 2018-03-20 |
| 9921895 | Transactional memory operations with read-only atomicity | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-20 |
| 9921834 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-03-20 |
| 9916239 | Multi-section garbage collection | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2018-03-13 |
| 9916186 | Managing processing associated with selected architectural facilities | Charles W. Gainey, Jr. | 2018-03-13 |
| 9916185 | Managing processing associated with selected architectural facilities | Charles W. Gainey, Jr. | 2018-03-13 |
| 9916180 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-13 |
| 9916179 | Interprocessor memory status communication | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-03-13 |
| 9910781 | Page table including data fetch width indicator | Jose E. Moreira, Balaram Sinharoy | 2018-03-06 |
| 9910769 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Christian Jacobi, Timothy J. Slegel | 2018-03-06 |
| 9904618 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Christian Jacobi, Timothy J. Slegel | 2018-02-27 |
| 9904572 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2018-02-27 |
| 9898296 | Selective suppression of instruction translation lookaside buffer (ITLB) access | Valentina Salapura | 2018-02-20 |
| 9898331 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Chung-Lung K. Shum, Timothy J. Slegel | 2018-02-20 |
| 9891919 | Caller protected stack return address in a hardware managed stack architecture | Karl J. Duvalsaint, Valentina Salapura | 2018-02-13 |
| 9892052 | Hybrid tracking of transaction read and write sets | Valentina Salapura, Chung-Lung K. Shum | 2018-02-13 |
| 9886252 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2018-02-06 |
| 9880835 | Initialization status of a register employed as a pointer | — | 2018-01-30 |
| 9880833 | Initialization status of a register employed as a pointer | — | 2018-01-30 |
| 9880821 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2018-01-30 |
| 9875082 | Single operation array index computation | — | 2018-01-23 |
| 9870210 | Partition mobility for partitions with extended code | Valentina Salapura | 2018-01-16 |