Issued Patents 2018
Showing 26–50 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10101997 | Independent vector element order and memory byte order controls | William J. Schmidt | 2018-10-16 |
| 10102007 | Simultaneously capturing status information for multiple operating modes | Brett Olsson | 2018-10-16 |
| 10095524 | Method and apparatus for dynamically replacing legacy instructions with a single executable instruction utilizing a wide datapath | Balaram Sinharoy | 2018-10-09 |
| 10095493 | Call sequence generation based on type of routine | — | 2018-10-09 |
| 10083113 | Scheme for determining data object usage in a memory region | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2018-09-25 |
| 10083134 | Configurable processor interrupts for allowing an application to independently handle interrupts | Giles R. Frazier | 2018-09-25 |
| 10083076 | Salvaging lock elision transactions with instructions to change execution type | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2018-09-25 |
| 10078515 | Tracking operand liveness information in a computer system and performing function based on the liveness information | Valentina Salapura | 2018-09-18 |
| 10073784 | Memory performance when speculation control is enabled, and instruction therefor | — | 2018-09-11 |
| 10073770 | Scheme for determining data object usage in a memory region | Giles R. Frazier, Younes Manton, Karl M. Taylor, Brian W. Thompto | 2018-09-11 |
| 10067716 | Inaccessibility status indicator | Brett Olsson | 2018-09-04 |
| 10061703 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-28 |
| 10061705 | Identifying instructions for decode-time instruction optimization grouping in view of cache boundaries | Valentina Salapura | 2018-08-28 |
| 10061572 | Reconfiguration of address space based on loading short pointer mode application | — | 2018-08-28 |
| 10061580 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | — | 2018-08-28 |
| 10061539 | Inaccessibility status indicator | Brett Olsson | 2018-08-28 |
| 10061586 | Latent modification instruction for transactional execution | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-28 |
| 10061588 | Tracking operand liveness information in a computer system and performing function based on the liveness information | Valentina Salapura | 2018-08-28 |
| 10055230 | Accurate tracking of transactional read and write sets with speculation | Valentina Salapura, Chung-Lung K. Shum | 2018-08-21 |
| 10055348 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-08-21 |
| 10042749 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-08-07 |
| 10042761 | Read and write sets for transactions of a multithreaded computing environment | Valentina Salapura | 2018-08-07 |
| 10042765 | Read and write sets for transactions of a multithreaded computing environment | Valentina Salapura | 2018-08-07 |
| 10025715 | Conditional inclusion of data in a transactional memory read set | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-07-17 |
| 10019357 | Supporting atomic accumulation with an addressable accumulator | Fadi Y. Busaba, Eric M. Schwarz | 2018-07-10 |