Issued Patents 2018
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157131 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2018-12-18 |
| 10152418 | Speculation control for improving transaction success rate, and instruction therefor | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-11 |
| 10127014 | Round for reround mode in a decimal floating point instruction | Michael F. Cowlishaw, Ronald M. Smith, Sr., Phil C. Yeh | 2018-11-13 |
| 10120803 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2018-11-06 |
| 10120802 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2018-11-06 |
| 10114752 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2018-10-30 |
| 10101998 | Vector checksum instruction | Jonathan D. Bradbury | 2018-10-16 |
| 10083008 | Reproducible stochastic rounding for out of order processors | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2018-09-25 |
| 10055348 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2018-08-21 |
| 10025715 | Conditional inclusion of data in a transactional memory read set | Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2018-07-17 |
| 10019357 | Supporting atomic accumulation with an addressable accumulator | Fadi Y. Busaba, Michael K. Gschwind | 2018-07-10 |
| 10013351 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2018-07-03 |
| 10013257 | Register comparison for operand store compare (OSC) prediction | David S. Hutton, Wen H. Li | 2018-07-03 |
| 9996346 | Multifunctional hexadecimal instruction form system and program product | Ronald M. Smith, Sr. | 2018-06-12 |
| 9996354 | Instruction stream tracing of multi-threaded processors | Lee Evan Eisen, Lisa C. Heller, Michael T. Huffer | 2018-06-12 |
| 9983904 | Multithreaded transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-05-29 |
| 9971628 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2018-05-15 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura +1 more | 2018-05-15 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2018-05-01 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2018-05-01 |
| 9952804 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more | 2018-04-24 |
| 9952943 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2018-04-24 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2018-04-17 |
| 9946494 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more | 2018-04-17 |
| 9940102 | Partial stochastic rounding that includes sticky and guard bits | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2018-04-10 |