Issued Patents 2018
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162743 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-12-25 |
| 10162744 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-12-25 |
| 10152418 | Speculation control for improving transaction success rate, and instruction therefor | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-12-11 |
| 10120803 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2018-11-06 |
| 10120802 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2018-11-06 |
| 10120681 | Compare and delay instructions | Charles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2018-11-06 |
| 10114752 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-10-30 |
| 10061703 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-08-28 |
| 10061586 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-08-28 |
| 10042749 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-08-07 |
| 10042642 | Generation and application of stressmarks in a computer system | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2018-08-07 |
| 10025592 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum | 2018-07-17 |
| 10025715 | Conditional inclusion of data in a transactional memory read set | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-07-17 |
| 10025589 | Conditional transaction end instruction | Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2018-07-17 |
| 10019265 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum | 2018-07-10 |
| 9996360 | Transaction abort instruction specifying a reason for abort | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2018-06-12 |
| 9983882 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Christian Jacobi, Robert R. Rogers | 2018-05-29 |
| 9983915 | Facilitating transaction completion subsequent to repeated aborts of the transaction | Brenton F. Belmar, Christian Jacobi, Randall W. Philley | 2018-05-29 |
| 9983883 | Transaction abort instruction specifying a reason for abort | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2018-05-29 |
| 9983881 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Christian Jacobi, Robert R. Rogers | 2018-05-29 |
| 9971629 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2018-05-15 |
| 9971690 | Transactional memory operations with write-only atomicity | Michael K. Gschwind, Chung-Lung K. Shum | 2018-05-15 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura +1 more | 2018-05-15 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz | 2018-05-01 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz | 2018-05-01 |