Issued Patents 2018
Showing 25 most recent of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162744 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-25 |
| 10162764 | Marking page table/page status table entries to indicate memory used to back address translation structures | Jonathan D. Bradbury | 2018-12-25 |
| 10162660 | Application-level processor parameter management | Giles R. Frazier | 2018-12-25 |
| 10162743 | Prefetch insensitive transactional memory | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-25 |
| 10162635 | Confidence-driven selective predication of processor instructions | — | 2018-12-25 |
| 10157131 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-12-18 |
| 10157119 | Configurable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2018-12-18 |
| 10152419 | Deferred response to a prefetch request | Valentina Salapura, Chung-Lung K. Shum | 2018-12-11 |
| 10152418 | Speculation control for improving transaction success rate, and instruction therefor | Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-12-11 |
| 10152338 | Marking external sibling caller routines | — | 2018-12-11 |
| 10152324 | Virtualization in a bi-endian-mode processor architecture | Brett Olsson | 2018-12-11 |
| 10146692 | Deferred response to a prefetch request | Valentina Salapura, Chung-Lung K. Shum | 2018-12-04 |
| 10140133 | Marking external sibling caller routines | — | 2018-11-27 |
| 10127155 | Memory performance when speculation control is enabled, and instruction therefor | — | 2018-11-13 |
| 10126976 | Integrating sign extensions for loads | — | 2018-11-13 |
| 10120803 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-11-06 |
| 10120804 | Hybrid tracking of transaction read and write sets | Valentina Salapura, Chung-Lung K. Shum | 2018-11-06 |
| 10120682 | Virtualization in a bi-endian-mode processor architecture | Brett Olsson | 2018-11-06 |
| 10120745 | Providing instructions to protect stack return addresses in a hardware managed stack architecture | Karl J. Duvalsaint, Valentina Salapura | 2018-11-06 |
| 10120802 | Transactional memory coherence control | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-11-06 |
| 10114752 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2018-10-30 |
| 10114971 | Interlinking routines with differing protections using stack indicators | — | 2018-10-30 |
| 10108407 | Loading optimized local entry points for local-use-only function pointers | Ulrich Weigand | 2018-10-23 |
| 10108406 | Linking optimized entry points for local-use-only function pointers | Ulrich Weigand | 2018-10-23 |
| 10108404 | Compiling optimized entry points for local-use-only function pointers | Ulrich Weigand | 2018-10-23 |