Issued Patents 2018
Showing 51–75 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10013258 | Single instruction array index computation | — | 2018-07-03 |
| 10013351 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2018-07-03 |
| 10013270 | Application-level initiation of processor parameter adjustment | Giles R. Frazier | 2018-07-03 |
| 9996326 | Layered vector architecture compatibility for cross-system portability | Ronald I. McIntosh | 2018-06-12 |
| 9997050 | Tracking a user based on an electronic noise profile | Valentina Salapura | 2018-06-12 |
| 9983904 | Multithreaded transactions | Fadi Y. Busaba, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-05-29 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Christian Jacobi, Valentina Salapura, Eric M. Schwarz +1 more | 2018-05-15 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9971690 | Transactional memory operations with write-only atomicity | Chung-Lung K. Shum, Timothy J. Slegel | 2018-05-15 |
| 9971629 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Chung-Lung K. Shum, Timothy J. Slegel | 2018-05-15 |
| 9971628 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2018-05-15 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959102 | Layered vector architecture compatibility for cross-system portability | Ronald I. McIntosh | 2018-05-01 |
| 9952844 | Executing optimized local entry points and function call sites | Ulrich Weigand | 2018-04-24 |
| 9952976 | Allowing non-cacheable loads within a transaction | Jonathan D. Bradbury, Valentina Salapura, Chung-Lung K. Shum | 2018-04-24 |
| 9952943 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2018-04-24 |
| 9952884 | Executing optimized local entry points and function call sites | Ulrich Weigand | 2018-04-24 |
| 9952862 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwartz, Timothy J. Slegel | 2018-04-24 |
| 9952804 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-24 |
| 9946521 | Programmable code fingerprint | Giles R. Frazier, Christian Jacobi, Chung-Lung K. Shum | 2018-04-17 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2018-04-17 |
| 9946494 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum +1 more | 2018-04-17 |
| 9940242 | Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries | Valentina Salapura | 2018-04-10 |
| 9940475 | Interlinking routines with differing protections using stack indicators | — | 2018-04-10 |