| 9928173 |
Conditional inclusion of data in a transactional memory read set |
Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel |
2018-03-27 |
| 9928032 |
Checksum adder |
James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. |
2018-03-27 |
| 9921872 |
Interprocessor memory status communication |
Dan F. Greiner, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel |
2018-03-20 |
| 9921895 |
Transactional memory operations with read-only atomicity |
Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel |
2018-03-20 |
| 9921834 |
Prefetching of discontiguous storage locations in anticipation of transactional execution |
Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more |
2018-03-20 |
| 9916179 |
Interprocessor memory status communication |
Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel |
2018-03-13 |
| 9916180 |
Interprocessor memory status communication |
Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel |
2018-03-13 |
| 9916159 |
Programmable linear feedback shift register |
Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky |
2018-03-13 |
| 9880811 |
Reproducible stochastic rounding for out of order processors |
Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky |
2018-01-30 |
| 9870254 |
Multithreaded transactions |
Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum |
2018-01-16 |
| 9864690 |
Detecting cache conflicts by utilizing logical address comparisons in a transactional memory |
Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel |
2018-01-09 |
| 9864692 |
Managing read tags in a transactional memory |
Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel |
2018-01-09 |
| 9858074 |
Non-default instruction handling within transaction |
Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum |
2018-01-02 |
