| 10157064 |
Processing of multiple instruction streams in a parallel slice processor |
Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-12-18 |
| 10083039 |
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices |
Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-09-25 |
| 9983878 |
Branch prediction using multiple versions of history data |
David S. Levitan, Mauricio J. Serrano |
2018-05-29 |
| 9977678 |
Reconfigurable parallel execution and load-store slice processor |
Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-05-22 |
| 9971602 |
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices |
Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-05-15 |
| 9952876 |
Optimize control-flow convergence on SIMD engine using divergence depth |
Gheorghe Almasi, Jessica Hui-Chun Tseng, Peng Wu |
2018-04-24 |
| 9928158 |
Redundant transactions for detection of timing sensitive errors |
Harold W. Cain, III, David M. Daly, Michael C. Huang, Kattamuri Ekanadham, Mauricio J. Serrano |
2018-03-27 |
| 9910781 |
Page table including data fetch width indicator |
Michael K. Gschwind, Balaram Sinharoy |
2018-03-06 |
| 9904551 |
Branch prediction using multiple versions of history data |
David S. Levitan, Mauricio J. Serrano |
2018-02-27 |
| 9898295 |
Branch prediction using multiple versions of history data |
David S. Levitan, Mauricio J. Serrano |
2018-02-20 |
| 9870229 |
Independent mapping of threads |
Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +1 more |
2018-01-16 |
