Issued Patents 2018
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140127 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-11-27 |
| 10133581 | Linkable issue queue parallel execution slice for a processor | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Hung Q. Le, Brian W. Thompto | 2018-11-20 |
| 10133576 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2018-11-20 |
| 10127121 | Operation of a multi-slice processor implementing adaptive failure state capture | Khandker N. Adeeb, Steven J. Battle, Brandon Goddard, Tu-An T. Nguyen, Nicholas R. Orzol +2 more | 2018-11-13 |
| 10127047 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-11-13 |
| 10120693 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Tu-An T. Nguyen, Salim A. Shah +1 more | 2018-11-06 |
| 10108423 | History buffer with single snoop tag for multiple-field registers | Michael J. Genden, Kenneth L. Ward | 2018-10-23 |
| 10102001 | Parallel slice processor shadowing states of hardware threads across execution slices | Kurt A. Feiste, Christopher M. Mueller, Eula A. Tolentino, Tien T. Tran, Jing Zhang | 2018-10-16 |
| 10078516 | Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-09-18 |
| 10073699 | Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture | Susan E. Eisen, Cliff Kucharski, Hung Q. Le, David R. Terry | 2018-09-11 |
| 10073697 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2018-09-11 |
| 10067766 | History buffer with hybrid entry support for multiple-field registers | Michael J. Genden | 2018-09-04 |
| 10067765 | Speeding up younger store instruction execution after a sync instruction | Susan E. Eisen, Hung Q. Le, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt +1 more | 2018-09-04 |
| 10067763 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2018-09-04 |
| 10055226 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le | 2018-08-21 |
| 10037259 | Adaptive debug tracing for microprocessors | Khandker N. Adeeb, Steven J. Battle, Brandon Goddard, Tu-An T. Nguyen, Nicholas R. Orzol +2 more | 2018-07-31 |
| 10031757 | Operation of a multi-slice processor implementing a mechanism to overcome a system hang | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Salim A. Shah | 2018-07-24 |
| 9996359 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Tu-An T. Nguyen, Salim A. Shah +1 more | 2018-06-12 |
| 9996353 | Universal history buffer to support multiple register types | Michael J. Genden, Hung Q. Le, Kenneth L. Ward | 2018-06-12 |
| 9985655 | Generating ECC values for byte-write capable registers | Dhivya Jeganathan, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2018-05-29 |
| 9983879 | Operation of a multi-slice processor implementing dynamic switching of instruction issuance order | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Salim A. Shah | 2018-05-29 |
| 9985656 | Generating ECC values for byte-write capable registers | Dhivya Jeganathan, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2018-05-29 |
| 9977677 | Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port | Kurt A. Feiste, Christopher M. Mueller, Eula Faye Abalos Tolentino, Tien T. Tran, Jing Zhang | 2018-05-22 |
| 9971687 | Operation of a multi-slice processor with history buffers storing transaction memory state information | Brian D. Barrick, Susan E. Eisen, Kurt A. Feiste, Kenneth L. Ward, Jing Zhang | 2018-05-15 |
| 9971604 | History buffer for multiple-field registers | Sundeep Chadha, Michael J. Genden, David R. Terry, Kenneth L. Ward | 2018-05-15 |