| 10073699 |
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture |
Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry |
2018-09-11 |
| 10067765 |
Speeding up younger store instruction execution after a sync instruction |
Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more |
2018-09-04 |
| 10055226 |
Thread transition management |
Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen |
2018-08-21 |
| 10048963 |
Executing system call vectored instructions in a multi-slice processor |
Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino |
2018-08-14 |
| 9971687 |
Operation of a multi-slice processor with history buffers storing transaction memory state information |
Brian D. Barrick, Kurt A. Feiste, Dung Q. Nguyen, Kenneth L. Ward, Jing Zhang |
2018-05-15 |
