| 10157064 |
Processing of multiple instruction streams in a parallel slice processor |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-12-18 |
| 10133581 |
Linkable issue queue parallel execution slice for a processor |
Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen, Brian W. Thompto |
2018-11-20 |
| 10133576 |
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries |
Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Dung Q. Nguyen +1 more |
2018-11-20 |
| 10083039 |
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-09-25 |
| 10073697 |
Handling unaligned load operations in a multi-slice computer processor |
Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more |
2018-09-11 |
| 10073699 |
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture |
Susan E. Eisen, Cliff Kucharski, Dung Q. Nguyen, David R. Terry |
2018-09-11 |
| 10067765 |
Speeding up younger store instruction execution after a sync instruction |
Susan E. Eisen, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more |
2018-09-04 |
| 10067763 |
Handling unaligned load operations in a multi-slice computer processor |
Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more |
2018-09-04 |
| 10055226 |
Thread transition management |
Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Dung Q. Nguyen |
2018-08-21 |
| 10042770 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions |
Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Elizabeth A. McGlone |
2018-08-07 |
| 10037229 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions |
Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Elizabeth A. McGlone |
2018-07-31 |
| 10037211 |
Operation of a multi-slice processor with an expanded merge fetching queue |
Kimberly M. Fernsler, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto |
2018-07-31 |
| 9998443 |
Retrospective discovery of shared credentials |
Aditya S. Cetlur, Edwin Boaz Soenaryo |
2018-06-12 |
| 9996353 |
Universal history buffer to support multiple register types |
Michael J. Genden, Dung Q. Nguyen, Kenneth L. Ward |
2018-06-12 |
| 9977678 |
Reconfigurable parallel execution and load-store slice processor |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-05-22 |
| 9971602 |
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2018-05-15 |
| 9940139 |
Split-level history buffer in a computer processing unit |
Dung Q. Nguyen, David R. Terry |
2018-04-10 |
| 9870229 |
Independent mapping of threads |
Sam Gat-Shang Chu, Markus Kaltenbach, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more |
2018-01-16 |
