Issued Patents 2018
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9971600 | Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-05-15 |
| 9965286 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-05-08 |
| 9959123 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-05-01 |
| 9959121 | Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers | Christopher M. Abernathy, Mary D. Brown, Sundeep Chadha | 2018-05-01 |
| 9952861 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-04-24 |
| 9952874 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-04-24 |
| 9940139 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2018-04-10 |
| 9928128 | In-pipe error scrubbing within a processor core | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Niels Fricke +1 more | 2018-03-27 |
| 9928073 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-03-27 |
| 9921833 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-03-20 |
| 9880850 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-01-30 |
| 9870039 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2018-01-16 |
| 9870231 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-01-16 |
| 9870229 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2018-01-16 |
| 9870045 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2018-01-16 |
| 9858078 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-01-02 |