Issued Patents 2018
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10002924 | Devices including high percentage SiGe fins formed at a tight pitch and methods of manufacturing same | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-06-19 |
| 10002794 | Multiple gate length vertical field-effect-transistors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-06-19 |
| 9997472 | Support for long channel length nanowire transistors | Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight | 2018-06-12 |
| 9997619 | Bipolar junction transistors and methods forming same | Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau | 2018-06-12 |
| 9991359 | Vertical transistor gated diode | Alexander Reznicek | 2018-06-05 |
| 9991168 | Germanium dual-fin field effect transistor | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-06-05 |
| 9984871 | Superlattice lateral bipolar junction transistor | Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-05-29 |
| 9972684 | Compressive strain semiconductor substrates | Pouya Hashemi, Nicolas Loubet, Alexander Reznicek | 2018-05-15 |
| 9953884 | Field effect transistor including strained germanium fins | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-24 |
| 9953973 | Diode connected vertical transistor | Pouya Hashemi, Alexander Reznicek | 2018-04-24 |
| 9947675 | Mask-programmable ROM using a vertical FET integration process | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-04-17 |
| 9947778 | Lateral bipolar junction transistor with controlled junction | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-04-17 |
| 9947775 | Replacement III-V or germanium nanowires by unilateral confined epitaxial growth | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-17 |
| 9947649 | Large area electrostatic dischage for vertical transistor structures | Pouya Hashemi, Alexander Reznicek, Jeng-Bang Yau | 2018-04-17 |
| 9941370 | Vertical field-effect-transistors having multiple threshold voltages | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-10 |
| 9935185 | Superlattice lateral bipolar junction transistor | Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-04-03 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9922942 | Support for long channel length nanowire transistors | Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight | 2018-03-20 |
| 9917179 | Stacked nanowire devices formed using lateral aspect ratio trapping | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9917175 | Tapered vertical FET having III-V channel | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9905649 | Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2018-02-27 |
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-02-20 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9893207 | Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-02-13 |