Issued Patents 2017
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852677 | Dithering for image data to be displayed | Seh Kwa | 2017-12-26 |
| 9831266 | Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same | James Kai, Johann Alsmeier, Jin Liu | 2017-11-28 |
| 9824966 | Three-dimensional memory device containing a lateral source contact and method of making the same | Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, James Kai, Yao-Sheng Lee | 2017-11-21 |
| 9812462 | Memory hole size variation in a 3D stacked memory | Liang Pang, Ashish Baraskar, Yingda Dong | 2017-11-07 |
| 9805662 | Content adaptive backlight power saving technology | — | 2017-10-31 |
| 9806089 | Method of making self-assembling floating gate electrodes for a three-dimensional memory device | Rahul Sharangpani, Somesh Peri, Raghuveer S. Makala | 2017-10-31 |
| 9805805 | Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof | Johann Alsmeier, James Kai | 2017-10-31 |
| 9799670 | Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof | Masatoshi Nishikawa, Jin Liu, Chun Ge | 2017-10-24 |
| 9779948 | Method of fabricating 3D NAND | Ashish Baraskar, Ching-Huang Lu, Zhenyu Lu | 2017-10-03 |
| 9748267 | Three dimensional NAND device with channel contacting conductive source line and method of making thereof | Go Shoji, Johann Alsmeier, Jayavel Pachamuthu, Yingda Dong, Jiahui Yuan | 2017-08-29 |
| 9748266 | Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof | Ashish Baraskar, Liang Pang, Ching-Huang Lu, Matthias Baenninger, Yingda Dong | 2017-08-29 |
| 9736443 | Adaptive image management of a projector system | — | 2017-08-15 |
| 9728546 | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same | Andrey Serov, James Kai, Henry Chien, Johann Alsmeier | 2017-08-08 |
| 9698153 | Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad | Jin Liu, Murshed Chowdhury, Raghuveer S. Makala, Johann Alsmeier | 2017-07-04 |
| 9691884 | Monolithic three dimensional NAND strings and methods of fabrication thereof | Raghuveer S. Makala, Rahul Sharangpani, Yao-Sheng Lee, Senaka Kanakamedala, George Matamis +1 more | 2017-06-27 |
| 9673213 | Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof | Jixin Yu, Zhenyu Lu, Johann Alsmeier, Daxin Mao | 2017-06-06 |
| 9672917 | Stacked vertical memory array architectures, systems and methods | Xiying Costa, Henry Chien, Yao-Sheng Lee | 2017-06-06 |
| 9672916 | Operation modes for an inverted NAND architecture | George Samachisa, Johann Alsmeier, Jian Chen | 2017-06-06 |
| 9646990 | NAND memory strings and methods of fabrication thereof | Sateesh Koka, Raghuveer S. Makala, Senaka Kanakamedala, Rahul Sharangpani, Yao-Sheng Lee +1 more | 2017-05-09 |
| 9627395 | Enhanced channel mobility three-dimensional memory structure and method of making thereof | Raghuveer S. Makala, Johann Alsmeier | 2017-04-18 |
| 9627399 | Three-dimensional memory device with metal and silicide control gates | Senaka Kanakamedala, Raghuveer S. Makala, Yao-Sheng Lee, George Matamis | 2017-04-18 |
| 9620514 | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same | James Kai, Henry Chien, Johann Alsmeier | 2017-04-11 |
| 9576971 | Three-dimensional memory structure having a back gate electrode | Johann Alsmeier, Yingda Dong, Akira Matsudaira | 2017-02-21 |
| 9576975 | Monolithic three-dimensional NAND strings and methods of fabrication thereof | James Kai, Raghuveer S. Makala, Jin Liu, Murshed Chowdhury, Camilla Huang +1 more | 2017-02-21 |
| 9570463 | Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same | Raghuveer S. Makala, Jin Liu, Murshed Chowdhury, Yao-Sheng Lee, Johann Alsmeier | 2017-02-14 |