Issued Patents 2017
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853109 | III-V MOSFET with self-aligned diffusion barrier | Cheng-Wei Cheng, Jack O. Chu, Yanning Sun, Jeng-Bang Yau | 2017-12-26 |
| 9852938 | Passivated germanium-on-insulator lateral bipolar transistors | Tak H. Ning, Jeng-Bang Yau | 2017-12-26 |
| 9799756 | Germanium lateral bipolar transistor with silicon passivation | Tak H. Ning, Jeng-Bang Yau | 2017-10-24 |
| 9773894 | Application of super lattice films on insulator to lateral bipolar transistors | Bahman Hekmatshoartabari, Tak H. Ning | 2017-09-26 |
| 9773865 | Self-forming spacers using oxidation | Masaharu Kobayashi, Effendi Leobandung | 2017-09-26 |
| 9752251 | Self-limiting selective epitaxy process for preventing merger of semiconductor fins | Eric C. Harley, Yue Ke, Annie Levesque | 2017-09-05 |
| 9711416 | Fin field effect transistor including a strained epitaxial semiconductor shell | Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park | 2017-07-18 |
| 9711417 | Fin field effect transistor including a strained epitaxial semiconductor shell | Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park | 2017-07-18 |
| 9698043 | Shallow trench isolation for semiconductor devices | Stephan A. Cohen, Alfred Grill, Deborah A. Neumayer | 2017-07-04 |
| 9691886 | Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base | Jin Cai, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau | 2017-06-27 |
| 9679967 | Contact resistance reduction by III-V Ga deficient surface | Takashi Ando, John Rozen, Jeng-Bang Yau, Yu Zhu | 2017-06-13 |
| 9679775 | Selective dopant junction for a group III-V semiconductor device | Marinus Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Deborah A. Neumayer +3 more | 2017-06-13 |
| 9673307 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2017-06-06 |
| 9659655 | Memory arrays using common floating gate series devices | Bahman Hekmatshoartabari, Tak H. Ning, Jeng-Bang Yau | 2017-05-23 |
| 9647099 | Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base | Jin Cai, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau | 2017-05-09 |
| 9590054 | Low temperature spacer for advanced semiconductor devices | Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang | 2017-03-07 |
| 9576964 | Integrated fin and strap structure for an access transistor of a trench capacitor | Babar A. Khan, Dae-Gyu Park, Xinhui Wang | 2017-02-21 |
| 9576096 | Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture | Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert +1 more | 2017-02-21 |
| 9564444 | Method of forming integrated fin and strap structure for an access transistor of a trench capacitor | Babar A. Khan, Dae-Gyu Park, Xinhui Wang | 2017-02-07 |
| 9553107 | Shallow extension junction | Pouya Hashemi, Effendi Leobandung, Dae-Gyu Park, Min Yang | 2017-01-24 |