Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847245 | Filling processes | Kyungseok Oh, Sung Min Kim | 2017-12-19 |
| 9831323 | Structure and method to achieve compressively strained Si NS | Ganesh Hegde, Robert C. Bowen, Borna J. Obradovic, Mark S. Rodder | 2017-11-28 |
| 9773886 | Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the same | Dharmendar Reddy Palle, Mark S. Rodder | 2017-09-26 |
| 9768062 | Method for forming low parasitic capacitance source and drain contacts | David Seo, Kota OIKAWA, Kim Changhwa, Rwik Sengupta, Mark S. Rodder | 2017-09-19 |
| 9698234 | Interface layer for gate stack using O3 post treatment | Mark S. Rodder, Wei-E Wang | 2017-07-04 |
| 9685509 | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions | Mark S. Rodder, Robert C. Bowen | 2017-06-20 |
| 9653287 | S/D connection to individual channel layers in a nanosheet FET | Mark S. Rodder, Joon Goo Hong, Borna J. Obradovic | 2017-05-16 |
| 9634140 | Fabricating metal source-drain stressor in a MOS device channel | Ganesh Hegde, Mark S. Rodder | 2017-04-25 |
| 9614002 | 0T bi-directional memory cell | Ryan M. Hatcher, Titash Rakshit, Borna J. Obradovic, Joon Goo Hong | 2017-04-04 |
| 9613907 | Low resistivity damascene interconnect | Ganesh Hegde, Mark S. Rodder, Robert C. Bowen | 2017-04-04 |
| 9601586 | Methods of forming semiconductor devices, including forming a metal layer on source/drain regions | Joon Goo Hong, Mark S. Rodder | 2017-03-21 |