Issued Patents 2017
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812370 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight | 2017-11-07 |
| 9786597 | Self-aligned pitch split for unidirectional metal wiring | Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe | 2017-10-10 |
| 9766220 | Leveraging air/water current variability for sensor network verification and source localization | Hendrik F. Hamann, Siyuan Lu, Ramachandran Muralidhar, Theodore G. van Kessel | 2017-09-19 |
| 9754965 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2017-09-05 |
| 9748404 | Method for fabricating a semiconductor device including gate-to-bulk substrate isolation | Michael A. Guillorn, Isaac Lauer, Xin Miao | 2017-08-29 |
| 9728624 | Semiconductor testing devices | Isaac Lauer, Jeffrey W. Sleight, Tenko Yamashita | 2017-08-08 |
| 9721888 | Trench silicide with self-aligned contact vias | Michael A. Guillorn, Fei Liu, Adam M. Pyzyna | 2017-08-01 |
| 9716219 | Suspended superconducting qubits | George A. Keefe, Chad Tyler Rigetti, Mary E. Rothwell | 2017-07-25 |
| 9716036 | Electronic device including moat power metallization in trench | Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna | 2017-07-25 |
| 9705063 | Sacrificial shorting straps for superconducting qubits | Douglas T. McClure, III | 2017-07-11 |
| 9684753 | Techniques for generating nanowire pad data from pre-existing design data | Karthik Balakrishnan, Michael A. Guillorn, Jeffrey W. Sleight | 2017-06-20 |
| 9653547 | Integrated etch stop for capped gate and method for manufacturing the same | Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao | 2017-05-16 |
| 9614270 | Superconducting airbridge crossover using superconducting sacrificial material | John M. Cotte | 2017-04-04 |
| 9564502 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2017-02-07 |
| 9564573 | Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits | Gerald W. Gibson, Mark B. Ketchen | 2017-02-07 |
| 9559284 | Silicided nanowires for nanobridge weak links | Paul Chang, Guy M. Cohen, Michael A. Guillorn | 2017-01-31 |
| 9559292 | Self-limited crack etch to prevent device shorting | Brian A. Bryce, Hiroyuki Miyazoe | 2017-01-31 |
| 9558930 | Mixed lithography approach for e-beam and optical exposure using HSQ | Szu-Lin Cheng, Isaac Lauer, Jeffrey W. Sleight | 2017-01-31 |
| 9536885 | Hybrid FINFET/nanowire SRAM cell using selective germanium condensation | Leland Chang, Isaac Lauer, Jeffrey W. Sleight | 2017-01-03 |
| 9536794 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2017-01-03 |