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Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device |
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Method of forming performance optimized gate structures by silicidizing lowered source and drain regions |
Katsunori Onishi, Jian-Shen Yu |
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Silicided nanowires for nanobridge weak links |
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