Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837319 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-12-05 |
| 9831084 | Hydroxyl group termination for nucleation of a dielectric metallic oxide | Takashi Ando, Michael P. Chudzik, Min Dai, Martin M. Frank, David F. Hilscher +3 more | 2017-11-28 |
| 9768071 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-09-19 |
| 9721843 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-08-01 |
| 9722045 | Buffer layer for modulating Vt across devices | Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Judson R. Holt | 2017-08-01 |
| 9685379 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-06-20 |
| 9620384 | Control of O-ingress into gate stack dielectric layer using oxygen permeable layer | Takashi Ando, Kai Zhao | 2017-04-11 |
| 9577061 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-02-21 |
| 9570354 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-02-14 |
| 9559010 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-01-31 |
| 9543213 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Jonathan T. Shaw | 2017-01-10 |