Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761679 | Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device | Paul Chang, Jian-Shen Yu | 2017-09-12 |
| 9735058 | Method of forming performance optimized gate structures by silicidizing lowered source and drain regions | Paul Chang, Jian-Shen Yu | 2017-08-15 |