GL

Gen P. Lauer

IBM: 11 patents #380 of 10,852Top 4%
TL Tokyo Electron Limited: 1 patents #266 of 744Top 40%
Overall (2017): #6,125 of 506,227Top 2%
11
Patents 2017

Issued Patents 2017

Patent #TitleCo-InventorsDate
9853210 Reduced process degradation of spin torque magnetoresistive random access memory Anthony J. Annunziata, Nathan P. Marchack, Stephen M. Rossnagel 2017-12-26
9812370 III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight 2017-11-07
9748310 Structure and method to reduce shorting in STT-MRAM device Anthony J. Annunziata, Nathan P. Marchack 2017-08-29
9705071 Structure and method to reduce shorting and process degradation in STT-MRAM devices Anthony J. Annunziata, Janusz J. Nowak, Eugene J. O'Sullivan 2017-07-11
9705077 Spin torque MRAM fabrication using negative tone lithography and ion beam etching Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Qinghuang Lin +1 more 2017-07-11
9691972 Low temperature encapsulation for magnetic tunnel junction Anthony J. Annunziata, Sebastian U. Engelmann, Eric A. Joseph, Nathan P. Marchack, Deborah A. Neumayer +1 more 2017-06-27
9673386 Structure and method to reduce shorting in STT-MRAM device Anthony J. Annunziata, Nathan P. Marchack 2017-06-06
9660179 Enhanced coercivity in MTJ devices by contact depth control Anthony J. Annunziata, Nathan P. Marchack 2017-05-23
9653679 Magnetoresistive structures with stressed layer Anthony J. Annunziata, Chandrasekharan Kothandaraman, Adam M. Pyzyna 2017-05-16
9601686 Magnetoresistive structures with stressed layer Anthony J. Annunziata, Chandrasekharan Kothandaraman, Adam M. Pyzyna 2017-03-21
9543388 Complementary metal-oxide silicon having silicon and silicon germanium channels Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight 2017-01-10