Issued Patents 2017
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853115 | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts | Shariq Siddiqui, Tenko Yamashita | 2017-12-26 |
| 9842933 | Formation of bottom junction in vertical FET devices | Kwan-Yong Lim, Steven Bentley, Daniel Chanemougame | 2017-12-12 |
| 9805986 | High mobility transistors | Manoj Mehrotra, Rick L. Wise | 2017-10-31 |
| 9779946 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2017-10-03 |
| 9780192 | Fringe capacitance reduction for replacement gate CMOS | Mahalingam Nandakumar | 2017-10-03 |
| 9779987 | Titanium silicide formation in a narrow source-drain contact | Min Gyu Sung, Kwanyong LIM | 2017-10-03 |
| 9735111 | Dual metal-insulator-semiconductor contact structure and formulation method | Takashi Ando, Tenko Yamashita | 2017-08-15 |
| 9721796 | Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget | James Joseph Chambers | 2017-08-01 |
| 9721847 | High-k / metal gate CMOS transistors with TiN gates | Brian K. Kirkpatrick | 2017-08-01 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | Steven Bentley, John H. Zhang, Kwan-Yong Lim | 2017-05-02 |
| 9640535 | Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices | Ruilong Xie | 2017-05-02 |
| 9589851 | Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs | Huiming Bu, Hui-feng Li, Vijay Narayanan, Tenko Yamashita | 2017-03-07 |
| 9576804 | System and method for mitigating oxide growth in a gate dielectric | Malcolm J. Bevan, Haowen Bu, Husam N. Alshareef | 2017-02-21 |
| 9543216 | Integration of hybrid germanium and group III-V contact epilayer in CMOS | Ruilong Xie | 2017-01-10 |