Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9747041 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera | 2017-08-29 |
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 9619396 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu | 2017-04-11 |
| 9606925 | Method, apparatus and system for optimizing cache memory transaction handling in a processor | Bahaa Fahim, Yen-Cheng Liu, Jeffrey D. Chamberlain, Min Huang | 2017-03-28 |