| 9753885 |
Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field |
Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek |
2017-09-05 |
| 9740654 |
Control messaging in multislot link layer flit |
Jeff Willey, Jeffrey C. Swanson |
2017-08-22 |
| 9740646 |
Early identification in transactional buffered memory |
Brian S. Morris, Bill Nale, Jeffrey C. Swanson |
2017-08-22 |
| 9729309 |
Securing data transmission between processor packages |
Simon P. Johnson, Abhishek Das, Carlos V. Rozas, Uday Savagaonkar, Kiran Padwekar |
2017-08-08 |
| 9697158 |
High performance interconnect physical layer |
Venkatraman Iyer, Darren S. Jue, Jeff Willey |
2017-07-04 |
| 9658963 |
Speculative reads in buffered memory |
Brian S. Morris, Bill Nale, Yen-Cheng Liu |
2017-05-23 |
| 9639490 |
Ring protocol for low latency interconnect switch |
Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati Srinivasa |
2017-05-02 |
| 9639276 |
Implied directory state updates |
— |
2017-05-02 |
| 9632862 |
Error handling in transactional buffered memory |
Brian S. Morris, Bill Nale, Eric L. Hendrickson |
2017-04-25 |
| 9626321 |
High performance interconnect |
Robert J. Safranek, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more |
2017-04-18 |
| 9619396 |
Two level memory full line writes |
Jeffrey D. Chamberlain, Yen-Cheng Liu, Vedaraman Geetha |
2017-04-11 |
| 9575895 |
Providing common caching agent for core and integrated input/output (IO) module |
Yen-Cheng Liu, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more |
2017-02-21 |
| 9552253 |
Probabilistic flit error checking |
Venkatraman Iyer, Debendra Das Sharma |
2017-01-24 |
| 9535838 |
Atomic operations in PCI express |
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more |
2017-01-03 |