Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824754 | Techniques for determining victim row addresses in a volatile memory | Sreenivas Mandava, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw +1 more | 2017-11-21 |
| 9747041 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Vedaraman Geetha, Henk G. Neefs, Sreenivas Mandava, Massimo Sutera | 2017-08-29 |
| 9740646 | Early identification in transactional buffered memory | Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson | 2017-08-22 |
| 9720838 | Shared buffered memory routing | Debendra Das Sharma, Michelle C. Jen | 2017-08-01 |
| 9658963 | Speculative reads in buffered memory | Bill Nale, Robert G. Blankenship, Yen-Cheng Liu | 2017-05-23 |
| 9632862 | Error handling in transactional buffered memory | Bill Nale, Robert G. Blankenship, Eric L. Hendrickson | 2017-04-25 |
| 9613722 | Method and apparatus for reverse memory sparing | George H. Huang, Debaleena Das, Rajat Agarwal | 2017-04-04 |