Issued Patents 2017
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9619396 | Two level memory full line writes | Robert G. Blankenship, Yen-Cheng Liu, Vedaraman Geetha | 2017-04-11 |
| 9606925 | Method, apparatus and system for optimizing cache memory transaction handling in a processor | Bahaa Fahim, Yen-Cheng Liu, Vedaraman Geetha, Min Huang | 2017-03-28 |
| 9563564 | Cache allocation with code and data prioritization | Andrew J. Herdrich, Edwin Verplanke, Ravishankar Iyer, Christopher C. Gianos, Ronak Singhal +2 more | 2017-02-07 |