Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9793159 | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace, Elliot N. Tan, Swaminathan Sivakumar | 2017-10-17 |
| 9793163 | Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects | Robert L. Bristol, Florian Gstrein, Richard E. Schenker, Charles H. Wallace, Hui Jae Yoo | 2017-10-17 |
| 9666451 | Self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace | 2017-05-30 |
| 9653576 | Patterning of vertical nanowire transistor channel and gate with directed self assembly | Swaminathan Sivakumar | 2017-05-16 |
| 9625815 | Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging | Eungnak Han, Swaminathan Sivakumar, Ernisse Putna | 2017-04-18 |