Issued Patents 2016
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530514 | Select gate defect detection | Jagdish Sabde, Sagar Magia | 2016-12-27 |
| 9524981 | Three dimensional memory device with hybrid source electrode for wafer warpage reduction | Johann Alsmeier | 2016-12-20 |
| 9524976 | Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device | Johann Alsmeier, Henry Chien | 2016-12-20 |
| 9520406 | Method of making a vertical NAND device using sequential etching of multilayer stacks | Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien | 2016-12-13 |
| 9515085 | Vertical memory device with bit line air gap | Peter Rabkin, Jilin Xia | 2016-12-06 |
| 9496274 | Three-dimensional non-volatile memory device | Johann Alsmeier, Raghuveer S. Makala, Yao-Sheng Lee | 2016-11-15 |
| 9478495 | Three dimensional memory device containing aluminum source contact via structure and method of making thereof | Peter Rabkin, Jilin Xia, Christopher J. Petti | 2016-10-25 |
| 9460931 | High aspect ratio memory hole channel contact formation | Johann Alsmeier, Raghuveer S. Makala, Yao-Sheng Lee | 2016-10-04 |
| 9455263 | Three dimensional NAND device with channel contacting conductive source line and method of making thereof | Yanli Zhang, Go Shoji, Johann Alsmeier, Yingda Dong, Jiahui Yuan | 2016-09-27 |
| 9449982 | Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks | Zhenyu Lu, Sateesh Koka, James Kai, Raghuveer S. Makala, Yao-Sheng Lee +2 more | 2016-09-20 |
| 9449985 | Memory cell with high-k charge trapping layer | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-09-20 |
| 9449981 | Three dimensional NAND string memory devices and methods of fabrication thereof | Johann Alsmeier, Henry Chien | 2016-09-20 |
| 9443861 | Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures | Ching-Huang Lu, Johann Alsmeier | 2016-09-13 |
| 9443865 | Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-09-13 |
| 9437606 | Method of making a three-dimensional memory array with etch stop | Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee, Masanori Terahara, Hirofumi Watatani | 2016-09-06 |
| 9425299 | Three-dimensional memory device having a heterostructure quantum well channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-08-23 |
| 9419135 | Three dimensional NAND device having reduced wafer bowing and method of making thereof | Matthias Baenninger, Johann Alsmeier | 2016-08-16 |
| 9406690 | Contact for vertical memory with dopant diffusion stopper and associated fabrication method | Liang Pang, Yingda Dong | 2016-08-02 |
| 9368510 | Method of forming memory cell with high-k charge trapping layer | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-06-14 |
| 9368509 | Three-dimensional memory structure having self-aligned drain regions and methods of making thereof | Liang Pang, Yingda Dong | 2016-06-14 |
| 9356031 | Three dimensional NAND string memory devices with voids enclosed between control gate electrodes | Yao-Sheng Lee, Raghuveer S. Makala, George Matamis, Johann Alsmeier, Henry Chien | 2016-05-31 |
| 9331093 | Three dimensional NAND device with silicon germanium heterostructure channel | Peter Rabkin | 2016-05-03 |
| 9287290 | 3D memory having crystalline silicon NAND string channel | Peter Rabkin, Johann Alsmeier, Masaaki Higashitani | 2016-03-15 |
| 9269446 | Methods to improve programming of slow cells | Sagar Magia, Jagdish Sabde, Ankitkumar Babariya | 2016-02-23 |
| 9240249 | AC stress methods to screen out bit line defects | Jagdish Sabde, Sagar Magia | 2016-01-19 |