Issued Patents 2016
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530506 | NAND boosting using dynamic ramping of word line voltages | Peter Rabkin, Yingda Dong | 2016-12-27 |
| 9530504 | Memory cells using multi-pass programming | Bo Lei, Gerrit Jan Hemink, Jun Wan, Zhenming Zhou | 2016-12-27 |
| 9472270 | Nonvolatile storage reflow detection | Guirong Liang, Changyuan Chen | 2016-10-18 |
| 9449985 | Memory cell with high-k charge trapping layer | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2016-09-20 |
| 9443597 | Controlling dummy word line bias during erase in non-volatile memory | Deepanshu Dutta, Mohan Dunga | 2016-09-13 |
| 9443907 | Vertical bit line wide band gap TFT decoder | Peter Rabkin | 2016-09-13 |
| 9443865 | Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2016-09-13 |
| 9425299 | Three-dimensional memory device having a heterostructure quantum well channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2016-08-23 |
| 9418751 | Pre-program detection of threshold voltages of select gate transistors in a memory device | Deepanshu Dutta, Shota Murai, Hideto Tomiie | 2016-08-16 |
| 9406781 | Thin film transistor | Peter Rabkin | 2016-08-02 |
| 9396808 | Method and apparatus for program and erase of select gate transistors | Deepanshu Dutta, Yan Li, Mohan Dunga | 2016-07-19 |
| 9368510 | Method of forming memory cell with high-k charge trapping layer | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2016-06-14 |
| 9368222 | Bit line pre-charge with current reduction | Mohan Dunga | 2016-06-14 |
| 9361986 | High endurance non-volatile storage | Jian Chen, Sergei Gorobets, Steven T. Sprouse, Tien-Chien Kuo, Yan Li +3 more | 2016-06-07 |
| 9349452 | Hybrid non-volatile memory cells for shared bit line | Mohan Dunga | 2016-05-24 |
| 9318533 | Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays | Pankaj Kalra, Chandrasekhar Gorla | 2016-04-19 |
| 9312015 | Methods for reducing body effect and increasing junction breakdown voltage | Chia-Lin Hsiung, Fumiaki Toyama | 2016-04-12 |
| 9287290 | 3D memory having crystalline silicon NAND string channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2016-03-15 |
| 9281317 | 3D non-volatile memory with metal silicide interconnect | Peter Rabkin | 2016-03-08 |
| 9245629 | Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Luca Fasoli, Roy E. Scheuerlein | 2016-01-26 |
| 9240420 | 3D non-volatile storage with wide band gap transistor decoder | Peter Rabkin | 2016-01-19 |