| 9520876 |
Power gating and clock gating in wiring levels |
Nathaniel R. Chadwick, Tassbieh Hassan, John E. Sheets, II, Christine Whiteside |
2016-12-13 |
| 9472269 |
Stress balancing of circuits |
Igor Arsovski, Nathaniel R. Chadwick, John Bradley Deforge, Ezra D. B. Hall |
2016-10-18 |
| 9437670 |
Light activated test connections |
Nathaniel R. Chadwick, John Bradley Deforge, John J. Ellis-Monaghan, Jeffrey P. Gambino, Ezra D. B. Hall +1 more |
2016-09-06 |
| 9405311 |
Bias-temperature induced damage mitigation circuit |
David M. Onsongo, David P. Paulsen, John E. Sheets, II |
2016-08-02 |
| 9401643 |
Bias-temperature induced damage mitigation circuit |
David M. Onsongo, David P. Paulsen, John E. Sheets, II |
2016-07-26 |
| 9383767 |
Circuit design for balanced logic stress |
Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Mack W. Riley |
2016-07-05 |
| 9378329 |
Immunity to inline charging damage in circuit designs |
Zachary Henderson, Jason D. Hibbeler, Terence B. Hook, Nicholas Palmer |
2016-06-28 |
| 9372208 |
Signal monitoring of through-wafer vias using a multi-layer inductor |
Mark A. DiRocco, Norman W. Robson, Keith C. Stevens |
2016-06-21 |
| 9316492 |
Reducing the impact of charged particle beams in critical dimension analysis |
Dongbing Shao |
2016-04-19 |
| 9299769 |
Semiconductor-on-oxide structure and method of forming |
John E. Barth, Jr., Herbert L. Ho, Babar A. Khan |
2016-03-29 |
| 9269642 |
Methods for testing integrated circuits of wafer and testing structures for integrated circuits |
Michael T. Coster, Mark A. DiRocco, Jeffrey P. Gambino |
2016-02-23 |
| 9250645 |
Circuit design for balanced logic stress |
Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Mack W. Riley |
2016-02-02 |
