Issued Patents 2016
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9383767 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, William Paul Hovis, Kirk D. Peterson, Mack W. Riley | 2016-07-05 |
| 9250645 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, William Paul Hovis, Kirk D. Peterson, Mack W. Riley | 2016-02-02 |