Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9383767 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson | 2016-07-05 |
| 9336105 | Evaluation of multiple input signature register results | — | 2016-05-10 |
| 9250645 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson | 2016-02-02 |