| 9530665 |
Protective trench layer and gate spacer in finFET devices |
Effendi Leobandung |
2016-12-27 |
| 9514992 |
Unidirectional spacer in trench silicide |
Emre Alptekin, Sameer H. Jain, Unoh Kwon, Zhengwen Li, Hari V. Mallela +3 more |
2016-12-06 |
| 9496148 |
Method of charge controlled patterning during reactive ion etching |
Sunit S. Mahajan, Bachir Dirahoui |
2016-11-15 |
| 9431395 |
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation |
Gregory Costrini, Ravikumar Ramachandran, Reinaldo Vega |
2016-08-30 |
| 9412654 |
Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step |
Junjing Bao, Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Yiheng Xu |
2016-08-09 |
| 9391020 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Akil Khamisi Sutton +2 more |
2016-07-12 |
| 9324793 |
Method for controlling the profile of an etched metallic layer |
Lawrence A. Clevenger, Carl Radens, Edem Wornyo, Yiheng Xu, John H. Zhang |
2016-04-26 |
| 9236447 |
Asymmetric spacers |
Kangguo Cheng, Ali Khakifirooz |
2016-01-12 |
