Issued Patents 2011
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8072070 | Low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Ching-Cheng Huang | 2011-12-06 |
| 8035227 | Top layers of metal for high performance IC's | Mou-Shiung Lin | 2011-10-11 |
| 8026588 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen, Mou-Shiung Lin | 2011-09-27 |
| 8022552 | Integrated circuit and method for fabricating the same | Mou-Shiung Lin | 2011-09-20 |
| 8022546 | Top layers of metal for high performance IC's | Mou-Shiung Lin | 2011-09-20 |
| 8021976 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen | 2011-09-20 |
| 8021918 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Chien-Kang Chou | 2011-09-20 |
| 8008776 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-08-30 |
| 8004083 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Chien-Kang Chou | 2011-08-23 |
| 8004088 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-08-23 |
| 7989954 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Chien-Kang Chou | 2011-08-02 |
| 7985653 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou | 2011-07-26 |
| 7977763 | Chip package with die and substrate | Mou-Shiung Lin, Ching-Cheng Huang | 2011-07-12 |
| 7973629 | Method for making high-performance RF integrated circuits | Mou-Shiung Lin | 2011-07-05 |
| 7969006 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Chien-Kang Chou | 2011-06-28 |
| 7964961 | Chip package | Hsin-Jung Lo | 2011-06-21 |
| 7960842 | Structure of high performance combo chip and processing method | Mou-Shiung Lin | 2011-06-14 |
| 7960212 | Structure of high performance combo chip and processing method | Mou-Shiung Lin | 2011-06-14 |
| 7960270 | Method for fabricating circuit component | Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo | 2011-06-14 |
| 7960272 | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging | Shih-Hsiung Lin | 2011-06-14 |
| 7932603 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-04-26 |
| 7923366 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-04-12 |
| 7919865 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-04-05 |
| 7919873 | Structure of high performance combo chip and processing method | Mou-Shiung Lin | 2011-04-05 |
| 7919867 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-04-05 |