Issued Patents 2011
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8022544 | Chip structure | Mou-Shiung Lin | 2011-09-20 |
| 8018060 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chien-Kang Chou | 2011-09-13 |
| 8013449 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2011-09-06 |
| 8008775 | Post passivation interconnection structures | Mou-Shiung Lin, Chien-Kang Chou | 2011-08-30 |
| 8004092 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Ching-San Lin | 2011-08-23 |
| 7985653 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Jin-Yuan Lee | 2011-07-26 |
| 7977803 | Chip structure with bumps and testing pads | Nick Kuo, Chien-Kang Chou, Chu-Fu Lin | 2011-07-12 |
| 7973401 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen | 2011-07-05 |
| 7964973 | Chip structure | Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo | 2011-06-21 |
| 7960269 | Method for forming a double embossing structure | Hsin-Jung Lo, Mou-Shiung Lin, Chien-Kang Chou | 2011-06-14 |
| 7947978 | Semiconductor chip with bond area | Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Ke-Hung Chen | 2011-05-24 |
| 7919412 | Over-passivation process of forming polymer layer over IC chip | Ying-Chih Chen, Mou-Shiung Lin | 2011-04-05 |
| 7880304 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2011-02-01 |