CC

Chien-Kang Chou

ME Megica: 16 patents #3 of 18Top 20%
📍 Baoshan, TW: #1 of 443 inventorsTop 1%
Overall (2011): #1,201 of 364,097Top 1%
16
Patents 2011

Issued Patents 2011

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
8021918 Integrated circuit chips with fine-line metal and over-passivation metal Mou-Shiung Lin, Jin-Yuan Lee 2011-09-20
8018060 Post passivation interconnection process and structures Mou-Shiung Lin, Chiu-Ming Chou 2011-09-13
8013449 Post passivation interconnection schemes on top of the IC chips Mou-Shiung Lin, Chiu-Ming Chou 2011-09-06
8008775 Post passivation interconnection structures Mou-Shiung Lin, Chiu-Ming Chou 2011-08-30
8004083 Integrated circuit chips with fine-line metal and over-passivation metal Mou-Shiung Lin, Jin-Yuan Lee 2011-08-23
8004092 Semiconductor chip with post-passivation scheme formed over passivation layer Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Ching-San Lin 2011-08-23
7989954 Integrated circuit chips with fine-line metal and over-passivation metal Mou-Shiung Lin, Jin-Yuan Lee 2011-08-02
7990037 Carbon nanotube circuit component structure Mou-Shiung Lin, Hsin-Jung Lo 2011-08-02
7985653 Semiconductor chip with coil element over passivation layer Wen-Chieh Lee, Mou-Shiung Lin, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee 2011-07-26
7977803 Chip structure with bumps and testing pads Nick Kuo, Chiu-Ming Chou, Chu-Fu Lin 2011-07-12
7969006 Integrated circuit chips with fine-line metal and over-passivation metal Mou-Shiung Lin, Jin-Yuan Lee 2011-06-28
7964973 Chip structure Mou-Shiung Lin, Chiu-Ming Chou, Hsin-Jung Lo 2011-06-21
7960270 Method for fabricating circuit component Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo 2011-06-14
7960269 Method for forming a double embossing structure Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou 2011-06-14
7932172 Semiconductor chip and process for forming the same Mou-Shiung Lin, Hsin-Jung Lo 2011-04-26
7880304 Post passivation interconnection schemes on top of the IC chips Mou-Shiung Lin, Chiu-Ming Chou 2011-02-01